In one embodiment, a method includes detecting a coupling of a device to an interface of the host machine. The method also includes determining, through an operating system of the host machine whether the device coupled to the interface of the host machine is same as another device that is...

The present disclosure describes techniques for scalable embedded memory programming. In some aspects data is received at a first communication interface from a host device, at least a portion of the data is stored to a memory device supported by a printed circuit board, and the data is transmitted to...

A peripheral apparatus management unit of an information processing apparatus includes an acquisition function for acquiring version information of an operating system. The unit further includes a selection function for selecting peripheral apparatus management function control information that defines information required to construct a view content of a peripheral apparatus...

A device comprising a router, a controller and an application processor, the controller configured to interoperate at any given time either with the controller or the application processor. When the device is coupled to a host device and the router is set for interoperating with the controller in which it...

A computer system including a data processing device for producing an image signal, an input device for producing a control signal and a display device is provided. The display device includes a memory unit, a controller, a source driver, a gate driver and a display panel. The controller is coupled...

An interface for an industrial controller is provided that enables connection of different types of plug-in I/O modules to the industrial controller. The interface includes several mechanisms, which can be implemented through control logic, circuitry, and/or software, that enable the control/monitoring device to operate in conjunction with different types of...

Disclosed herein is a system for monitoring high speed interchip (HSIC) universal serial bus (USB) signals in a device comprising a USB controller configured to output first USB transceiver macro-cell (UTMI+) signals, an HSIC PHY transceiver configured to receive first UTMI+ signals from the USB controller and to convert and...

A method of operating a microphone system includes the steps of monitoring an I/O terminal to detect whether a signal on that terminal achieves a pre-defined logic level during a monitoring period. The I/O terminal and a second I/O terminal are configured to one of a hardware mode or a...

According to one embodiment, a data processing circuit included in a data processing apparatus together with plural peripheral circuits including a peripheral circuit configured to output first data includes a processing unit and a stop unit. The processing unit subjects the first data to data processing according to a specified...

A communication speed control apparatus for controlling communication between a host device and an external device in accordance with a high-speed communication mode or a low-speed communication mode includes a list storage unit configured to store a list of specification information of external devices that are incompatible with the host...

Provided is an apparatus for processing a key input using an interrupt. When a key is pressed, a key input signal and a key interrupt signal may be generated and transmitted to a control unit which may process the pressed input key. When the control unit receives the key interrupt...

A method for dynamically enabling and disabling use of XFR_RDY is disclosed herein. In one embodiment of the invention, such a method includes receiving a write command at a target and determining whether XFR_RDY is enabled or disabled for the write command. In the event XFR_RDY is disabled, the method...

A buffer management mechanism in a multi-core processor for use on a modem in a telecommunications network is described herein. The buffer management mechanism includes a buffer module that provides buffer management services for one or more Layer 2 applications, wherein the buffer module at least provides a user space...

A data processing apparatus may include a buffer unit, a data write control unit, a data read control unit, and a buffer area determination unit. The data write control unit may write the input data to the storage area determined by the buffer area determination unit, and output a data...

A method and communication system that provide an inexpensive approach that enables the times of events that are detected in IO device to be determined in a higher-level controller. The higher-level controller has a system clock and is connected to an IO link device to which multiple first IO devices...

A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts...

The invention concerns a device for transmitting data between a serial data bus and working modules, wherein the data bus is connected to a bus node in a bus module having at least two serial communication ports which are connected to ports of a hub connected to or integrated with...

A physiological data collection device obtains physiological data from a subject interface on a subject. The physiological data collection device includes a data connector such as a USB connector for connecting directly to a computer. When the physiological data collection device is connected to the computer, the physiological data is...

A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control...

In an information-processing apparatus including a plurality of modules and a first arbiter which arbitrates bus-access requests of the plurality of modules, at least one of the plurality of modules includes a plurality of submodules and a second arbiter which arbitrates bus-access requests of the plurality of submodules and transmits...