OTTAWA and SANTA CLARA, CA -- (Marketwire) -- 01/30/13 --
Sidense exhibiting at the Common Platform Technology Forum and presenting its 1T-OTP non-volatile memory IP spanning a wide range of process nodes (180nm to 28nm), including HV and BCD variants.
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, California 95054
Tuesday, February 5, 2013
11:30AM to 6:00PM
Xerxes Wania, President and CEO
Jim Lipman, Marketing Director
For more information or to schedule a meeting with Sidense please contact:
Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required. The Company's innovative one-transistor 1T-Fuse architecture provides the industry's smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (LNVM) IP solution. With 94 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense SiPROM, SLP and ULP memory products, embedded in more than 250 customer designs, are available from 180nm down to 28nm and are scalable to 20nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, please visit www.sidense.com
About the Common Platform Technology Forum
At the Common Platform Technology Forum, you will see and hear firsthand how the combined expertise of our partners is addressing the most demanding IC design and manufacturing challenges. Our collaborative research and innovative technology development have resulted in an accelerated roadmap and rapid customer adoption, and we'll touch upon these key highlights: leading-edge process technologies at 32/28-, 20-, 14-nanometer, and beyond; advanced innovations such as FinFet, design & technology co-optimization, and double patterning. You will get a peek into the future of next-generation device innovations being researched, including silicon nanowires, carbon nanotubes, and 3D device structures. Also visit the Partner Pavilion for a showcase of our Ecosystem Partner and Common Platform design, enablement, and implementation offerings.