Wednesday, July 23, 2014 Last update: 6:33 PM
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Aldec Presents a Visual Mapping Solution to Capture a Bird’s-eye View of UVM Verification Environments

Companies mentioned in this article: Aldec, Inc.

HENDERSON, Nev. -- (BUSINESS WIRE) -- Aldec, Inc., announces the latest release of its mixed-language, advanced verification platform, Riviera-PRO™ 2014.02. The new release offers an enhanced debugging tool suite featuring UVM Graph which delivers the unique ability to visualize a UVM verification environment. This latest enhancement to Riviera-PRO provides a graphic solution to what was once a challenging task, visualizing the testbench architecture and data flow between UVM components.

“Debugging within a UVM verification environment can be a complex task without full understanding of the testbench architecture and data flow,” said Satyam Jani, Product Manager, Aldec Software Division, “With UVM Graph, users can now visualize from the top-down as the architecture of the UVM-based testbenches is now displayed in an easy-to-understand, graphical format.”

UVM Graph maps the UVM component and Objects, as well as the Transaction Level Modeling (TLM) connections between them, helping users gain an overall understanding of the testbench architecture and dataflow. Debugging within a UVM environment is further simplified by integrating an HDL Editor, Classes and Objects window for each component on the UVM Graph to enable the pinpointing of specific issues.

Combined with Class- and Transaction-Visualization tools, Riviera-PRO provides a comprehensive solution for advanced verification using UVM libraries. In addition, the 2014.02 release of Riviera-PRO also includes numerous new features, enhancements, and performance optimizations.

For additional information about Riviera-PRO 2014.02 including tutorials, free evaluation downloads and What’s New Presentation, please visit http://www.aldec.com/Products/Riviera-PRO.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com

Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.


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Contact:

Aldec, Inc.
Christina Toole, + (702) 990-4400
christinat@aldec.com