ALAMEDA, CA -- (Marketwired) -- 06/03/15 --
WHO: Verific Design Automation, provider of SystemVerilog, VHDL and UPF parsers
WHAT: Invites attendees of the 52nd Design Automation Conference (DAC) to stop by its booth (#2714) to pick up this year's giraffe giveaway and learn more about its SystemVerilog, Verilog, VHDL and UPF parser platforms. Verific's software is used by electronic design automation (EDA) companies, including 24 exhibiting at DAC, as the front end for their analysis, emulation, simulation, synthesis and verification tools.
WHEN: ... read more